[Verilog HDL] 실습2
FSM module traffic_fsm (nRST, CLK, RO, GO, LO, YO); input nRST, CLK; output RO, GO, LO, YO; reg RO, GO, LO, YO; parameter RED = 0; parameter GRN = 1; parameter LEF = 2; parameter YEL = 3; reg state_en; reg [4:0] state_cnt; reg [1:0] CS_state; // current state reg [1:0] NS_state; // next state // state enable counter always@(negedge nRST or posedge CLK) if(!nRST) state_cnt
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