본문 바로가기

System verilog

[SV] Data type

  • Structural

wire, reg

 

  • Behavioral

integer, real, time, logic

- integer : -2^31 to (2^31 -1)

- real : 64bit real number decimal, scientific notation // ex) 14.72 , 1.2e3

- time : conjunction with the $time system task to hold simulation time. not supported for synthesis

- logic : 

             bit                             – Unsigned
                    byte, shortint, int, longint    – Signed
                       unsigned two-state types,
                          bit            single_bit ;    // unsigned single bit
                          bit [31:0]     32_bit      ;    // 32-bit unsigned integer
                       signed two-state types,
                          int           integer;   // 32-bit signed integer
                          byte          8_bit  ;   //   8-bit signed integer
                          shortint      16_bit ;   // 16-bit signed integer
                          longint       64_bit ;   // 64-bit signed integer
                       unsigned from signed two-state types,
                           int           unsigned integer;   // 32-bit unsigned integer
                           byte          unsigned  8_bit;   //   8-bit unsigned integer
                           shortint      unsigned  16_bit;   // 16-bit unsigned integer
                           longint       unsigned  64_bit;   // 64-bit unsigned integer

 

  • Void 

non-existent data, no return value

- void'(function_call());

 

  • String

ex) string  s1 = "Hellow World";

      string  s2 = {"Hi"," ",s1}; // empty string " "

      bit [11:0] b = 12'ha41;

      string  s3 = string'(b); // sets s3 to 16'h0a41, 8bit 의 배수로 assign

 

  • Event

- define : event <event_name>;

- triggering : -> event_name;

- waiting : @ event_name; or wait (event_name.triggered);

 

  • User-defined 

typedef data_type new_type_identifier

ex)  bit [7:0] my_byte;

       typedef bit [7:0] ubyte;  // alias와 비슷한 개념

       ubyte my_byte; 

 

  • Enumerated 

enum [enum base type] {enum_name_declarations} variable_name;

- base_type이 non-declare 시 int type.

- number가 지정되지 않은 enum_name은 앞에 숫자에서 자동으로 증가된 숫자가 assign 됩니다.

ex) 

enum {red, green, blue=4, yellow, white=8, black} Colors;

initial begin

  Colors = Colors.first; // Colors = red : 0

  $display("Colors Value of %0s \t is = %0d", Colors.name, Colors); //%0s = red / %0d = 0

  Colors = Colors.next; // Colors = green : 1

  Colors = Colors.last;  // Colors = balck : 9, white is 8 >> + 1

 

if) red = 1, blue =2 ==> Error : blue is duplicate of enum label 'green' 

 

  • Class

ex) 

class packet;

  // Properties

  bit [31:0] address;

  bit [31:0] data;

 

   // Method

  function new();

    $display("Inside new Function of packet");

  endfunction

endclass : packet

 

'System verilog' 카테고리의 다른 글

[SV] Class  (0) 2022.12.15
[SV] event / concurrency  (0) 2022.12.15
[SV] Do while loop  (0) 2022.12.15
[SV] Arrays  (0) 2022.12.14