System verilog 썸네일형 리스트형 [SV] Class declaration ex) property, method class sv_class; //class properties int x; //method-1 task set(int i); x = i; endtask //method-2 function int get(); return x; endfunction endclass module sv_class_ex; sv_class class_1; //Creating Handle initial begin sv_class class_2 = new(); //Creating handle and Object class_1 = new(); //Creating Object for the Handle //Accessing Class methods class_1.set(10); .. 더보기 [SV] event / concurrency iff in event control example module event_ctrl; bit clk; bit reset; always #2 clk = ~clk; //at posedge of clk if reset is equals to '0',always block will be executed always @(posedge clk iff reset == 0) begin :block-1 $display($time,"\tInside always block"); end :block-1 //always block will be executed at every posedge and negedge of clk signal always @(posedge reset or negedge reset) begin :blo.. 더보기 [SV] Do while loop do - while do begin end while (expression); ex) int a; initial begin do begin $display("\t Value of a=%0d",a); a++; end while(a5) end // a = 0 if, a = 0 a = 1 a = 2 a = 3 a = 4 더보기 [SV] Arrays Packed / Unpacked Packed : vector를 access가 용이하도록 subfield로 나눈 구조 dimension declared before the data identifier name => packed : contiguous dimension declared after the data identifier name => unpacked : non-contiguous ex) bit [2:0] [7:0] array1; ==> packed bit [2:0] array2 [7:0]; ==> unpacked Dynamic data_type array_name []; - methods new[] => allocates the storage size() => returns the current .. 더보기 [SV] Data type Structural wire, reg Behavioral integer, real, time, logic - integer : -2^31 to (2^31 -1) - real : 64bit real number decimal, scientific notation // ex) 14.72 , 1.2e3 - time : conjunction with the $time system task to hold simulation time. not supported for synthesis - logic : bit – Unsigned byte, shortint, int, longint – Signed unsigned two-state types, bit single_bit ; // unsigned single bit b.. 더보기 이전 1 다음
